A repository of stochastic arithmetic units for reproducible research.
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There are: 4 implementations for this unit
Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz A Fair Comparison of Adders in Stochastic Regime 2017 27th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) PDF Bibtex
@INPROCEEDINGS{8106990,
author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}},
booktitle={2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
title={A fair comparison of adders in stochastic regime},
year={2017},
volume={},
number={},
pages={1-6},
keywords={adders;logic design;low-power electronics;stochastic processes;error tolerant adder type II;power-efficient systems;approximate circuits;stochastic techniques;approximate arithmetic units;arithmetic circuits;adders;Adders;Computer architecture;Stochastic processes;Generators;Delays},
doi={10.1109/PATMOS.2017.8106990},
ISSN={},
month={Sep.},}