A repository of stochastic arithmetic units for reproducible research.
None
There are: 4 implementations for this unit
Ardalan Najafi, Moritz Weissbrich, Guillermo Paya Vaya and Alberto Garcia-Ortiz A Fair Comparison of Adders in Stochastic Regime 2017 27th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) PDF Bibtex
@INPROCEEDINGS{8106990,
author={A. {Najafi} and M. {Weissbrich} and G. {Paya-Vaya} and A. {Garcia-Ortiz}},
booktitle={2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
title={A fair comparison of adders in stochastic regime},
year={2017},
volume={},
number={},
pages={1-6},
keywords={adders;logic design;low-power electronics;stochastic processes;error tolerant adder type II;power-efficient systems;approximate circuits;stochastic techniques;approximate arithmetic units;arithmetic circuits;adders;Adders;Computer architecture;Stochastic processes;Generators;Delays},
doi={10.1109/PATMOS.2017.8106990},
ISSN={},
month={Sep.},}
Ning Zhu, Wang Ling Goh, Kiat Seng Yeo An enhanced low-power high-speed Adder For Error-Tolerant application 2009 Proceedings of the 12th International Symposium on Integrated Circuits PDF Bibtex
@INPROCEEDINGS{5403865,
author={ {Ning Zhu} and W. L. {Goh} and K. S. {Yeo}},
booktitle={Proceedings of the 2009 12th International Symposium on Integrated Circuits},
title={An enhanced low-power high-speed Adder For Error-Tolerant application},
year={2009},
volume={},
number={},
pages={69-72},
keywords={adders;integrated circuit design;VLSI;enhanced low-power high-speed adder;VLSI technology;test-error-tolerance;error-tolerant adder;power consumption;power delay product;Adders;Very large scale integration;Digital systems;Integrated circuit noise;Energy consumption;Power engineering and energy;Electronic mail;Degradation;Circuit testing;High speed integrated circuits;Adders;error-tolerance;high speed integrated circuits;low power design},
doi={},
ISSN={2325-0631},
month={Dec},}