Introduction to Microlectronics
Tutorial IR Drops

In modern integrated circuit (IC) design, ensuring robust power delivery is essential to meet performance, timing, and reliability goals. One of the critical checks in this domain is IR drop analysis — the process of evaluating voltage drops across the power delivery network due to the resistance (R) and current (I) in metal interconnects. IR drops, if not properly managed, can lead to:

• Timing violations (due to reduced voltage at critical cells),
• Functional errors (if the voltage drops below logic thresholds),
• Reduced reliability (from long-term stress on transistors).

This tutorial focuses on Cadence Voltus IC Power Integrity Solution, a powerful tool for analyzing dynamic and static IR drop, electromigration (EM), and power grid robustness. You'll learn how to:

• Perform static and dynamic IR drop checks,
• Visualize and debug IR hotspots

Static power analysis in Voltus focuses on estimating and verifying the power consumed by a design when it is not switching—primarily due to leakage currents. This includes contributions from subthreshold leakage, gate leakage, and junction leakage, which become increasingly significant in advanced technology nodes.

Run the following line in order to run the tool:

voltus -log log/log

This following commands set up a multi-core environment for faster processing and loads technology and cell LEF files required for physical design. It then reads in the timing views, Verilog netlist, and routed DEF file to initialize the design database for the Rocket top module.

Paste this in the voltus command line:

set_multi_cpu_usage \
	-localCpu                       8

set lefs [list]
lappend lefs ../Library/lef/gsclib045_tech.lef
lappend lefs ../Library/lef/gsclib045_tech_width.lef
lappend lefs ../Library/lef/gsclib045_macro.lef
lappend lefs ../Library/lef/gsclib045_lvt_macro.lef
lappend lefs ../Library/lef/gsclib045_hvt_macro.lef
read_lib -lef $lefs

read_view_definition mmmc.view

read_verilog rocket.v
set_top_module Rocket -ignore_undefined_cell

read_def ./results/design_Rocket/routeopt/routeopt.def.gz

The SPEF (Standard Parasitic Exchange Format) file provides detailed parasitic resistance and capacitance data for interconnects in the design, which is used for accurate timing and power analysis.

read_spef \
    -rc_corner                  RC_wc_125 \
    -decoupled			\
				lib_lef/Rocket_RC_wc_125.spef.gz

Now we reset the power analysis mode and then configure Voltus to perform static power analysis using the func_wc (functional worst-case) views for both leakage and dynamic power. It also enables writing of static current data and generates a binary database (staticPower.db) to store the analysis results using the static method.

set_power_analysis_mode \
    -reset

set_power_analysis_mode \
    -leakage_power_view 	func_wc \
    -dynamic_power_view        	func_wc \
    -write_static_currents      true \
    -binary_db_name             staticPower.db \
    -create_binary_db           true \
    -method                     static 

Now we set the switching activity values on the rst input port and on the output pins of cells, then propagate these activities through the design to simulate dynamic power behavior.

set_switching_activity \
    -reset

set_switching_activity \
    -input_port                 rst \
    -activity                   0.99 \
    -duty                       0.95

propagate_activity

get_activity \
    -port                       rst

set_switching_activity \
    -pin [ \
	get_pins -of_objects [ \
	    get_cells RC_CGIC* -hierarchical \
	] \
	-filter "@direction == out" \
    ] \
    -activity                   0.9

propagate_activity

get_activity \
    -pin [ \
	get_pins -of_objects [ \
	    get_cells RC_CGIC* -hierarchical \
	] \
	-filter "@direction == out" \
    ]

set_default_switching_activity \
    -input_activity             0.9 \
    -global_activity            0.95 \
    -period                     4.0 \
    -clock_gates_output_ratio   0.1

We define the output directory for storing static power analysis results and run the power analysis, saving the report to static.rpt. Then we read the generated power database and set up a graphical plot to visualize instance-level power consumption, specifically for IP blocks.

set_power_output_dir            staticPowerResults

report_power \
    -outfile                    static.rpt


read_power_rail_results \
    -power_db                   staticPowerResults/staticPower.db

set_power_rail_display \
    -plot ip

The following set_power_rail_display commands configure different visualization plots for analyzing power data in Voltus. The first plot shows the filtered instance power, highliting specific instances. The second plot displays the operating frequency of instances. The third plot visualizes the transition density, indicating how frequently signals are switching. The final command clears any active plots from the display.

set_power_rail_display \
    -plot                       ip \
    -filter_max 		0.0038 \
    -filter_min			1.00001e-05

set_power_rail_display \
    -plot                       freq 

set_power_rail_display \
    -plot                       td

set_power_rail_display \
    -plot                       none

Static Rail Analysis is a critical step in verifying the integrity of a chip's power delivery network by analyzing the IR (voltage) drop across the power rails under worst-case static conditions. Unlike Static Power Analysis, which estimates the power consumed by a design (including leakage and dynamic components) based on switching activities and library data, Static Rail Analysis focuses on how well the power grid can maintain voltage levels across the chip during operation.

It uses current demands derived from static power analysis and propagates them through the resistive network of the power grid to determine voltage drops. The goal is to ensure that the supply voltage delivered to all parts of the chip remains within acceptable limits to avoid timing failures or functional errors.

set_rail_analysis_mode \
    -method                     static \
    -accuracy                   xd \
    -analysis_view              func_wc\
    -power_grid_library         { \
	../Library/pgv/techonly.cl \
	../Library/pgv/stdcells.cl \
    } \
    -enable_rlrp_analysis       true \
    -verbosity true \
    -temperature 125

Now we define the power (VDD) and ground (VSS) nets for rail analysis, assigning them their expected voltages and acceptable threshold limits for IR drop violations. The -threshold values specify the voltage limits below (for VDD) or above (for VSS) which a violation is flagged, and these thresholds can be adjusted by the user depending on how strict or relaxed the voltage margin requirements are for the design.

set_pg_nets -net VDD     -voltage 0.9 -threshold 0.89 -force
set_pg_nets -net VSS     -voltage 0.0 -threshold 0.01 -force
set_rail_analysis_domain -name ALL -pwrnets VDD -gndnets VSS

We specify the location of power (VDD) and ground (VSS) pads by reading coordinate data from external .pp files, which define pad positions in xy format. These pad files are typically generated by the physical implementation tool (like Innovus) and are essential for accurately modeling current flow into the power grid during rail analysis.

set_power_pads \
    -reset

set_power_pads \
    -net                        VDD \
    -format                     xy \
    -file                       VDD.pp

set_power_pads \
    -net                        VSS \
    -format                     xy \
    -file                       VSS.pp

The last step is to load the average current data (ptiavg files) for the VDD and VSS nets, which was generated during static power analysis, and use it in the rail analysis. Then we start the static rail analysis, outputting results to the specified ./staticRailResults directory.

set_power_data -reset
set_power_data \
    -format                     current \
    { \
	staticPowerResults/static_VDD.ptiavg \
	staticPowerResults/static_VSS.ptiavg \
    }

analyze_rail \
    -output           ./staticRailResults \
    -type                       domain \
				ALL

The IR drops are now categorized and result in a distribution. This depends on the activity of the data within the chip and the resulting power demand. You find this report in ./staticRailResults/ALL_125C_avg_1/VDD/results

We see the difference, when we change the -global_activity to a smaller value of 0.2. We get the following result:

set_default_switching_activity \
    -input_activity             0.1 \
    -global_activity            0.1 \
    -period                     0.01 \
    -clock_gates_output_ratio   0.1


report_power \
    -outfile                    static.rpt


analyze_rail \
    -output           ./staticRailResults \
    -type                       domain \
				ALL

Dynamic power analysis focuses on the power consumed due to signal switching activities within a design during its functional operation. Unlike static power analysis, which estimates leakage power under fixed conditions, dynamic analysis accounts for real input stimuli, timing, and toggling rates, providing a more accurate view of power usage across various modes. This helps identify power-hungry regions, optimize switching activity, and improve overall energy efficiency of the chip.

You can open a new terminal and run voltus:

voltus -log log/log

The preparation of the tool is very similar to the static case. We have to load files such as LEF, SPEF, DEF etc.

set lefs [list]
lappend lefs ../Library/lef/gsclib045_tech.lef
lappend lefs ../Library/lef/gsclib045_tech_width.lef
lappend lefs ../Library/lef/gsclib045_macro.lef
lappend lefs ../Library/lef/gsclib045_hvt_macro.lef
lappend lefs ../Library/lef/gsclib045_lvt_macro.lef

read_lib -lef $lefs


read_view_definition mmmc.view

read_verilog rocket.v
set_top_module Rocket -ignore_undefined_cell

read_def ./results/design_Rocket/routeopt/routeopt.def.gz


read_spef \
    -rc_corner                  RC_wc_125 \
    -decoupled				\
				    ./lib_lef/Rocket_RC_wc_125.spef.gz

You should see something like this:

We perform a dynamic vectorless power analysis in Voltus, using estimated switching activity and a defined current waveform for a specific instance. The results are written to a report and a power database.

set_power_output_dir            dynVecLessPowerResults

set_power_analysis_mode \
    -reset

set_power_analysis_mode \
    -analysis_view              func_wc\
    -disable_static             false \
    -write_static_currents      true \
    -binary_db_name             dynPower.db \
    -create_binary_db           true \
    -method                     dynamic_vectorless 

set_power \
    -reset

set_power \
    -pg_net                     VDD \
    -pwl \
    -instance                   alu_sra_4458_52_g4770 { \
	0ns      0mA \
	0.075ns  0mA \
	0.175ns 45mA \
	0.225ns 15mA \
	0.425ns  0mA \
    } \
    -sticky


set_dynamic_power_simulation \
    -reset

set_dynamic_power_simulation \
    -resolution                 50ps

report_power \
    -outfile                    dyn.rpt

We display the dynamic current waveform for the specified instance (alu_sra_4458_52_g4770) using data from the given .ptiavg file, allowing visual inspection of power behavior over time.

view_dynamic_waveform \
   -type                        current \
   -instance_name                alu_sra_4458_52_g4770\
   -waveform_files              {dynVecLessPowerResults/dynamic_VDD.ptiavg}

The following command displays the total composite current waveform across the entire VDD net using the .ptiavg file — giving a broader view of dynamic current consumption in the design.

view_dynamic_waveform \
   -type current \
   -composite_waveform_type total_current \
   -waveform_files { dynVecLessPowerResults/dynamic_VDD.ptiavg }

Dynamic rail analysis evaluates voltage drops and power integrity under time-varying conditions, capturing how switching activity and transient currents impact the power grid during real operation.

This command configures Voltus for dynamic rail analysis using the worst-case functional view (func_wc), enabling power switch and decap ECO generation, saving voltage waveforms, and preparing graphical output based on the specified power grid libraries:

set_rail_analysis_mode \
    -method                     dynamic \
    -analysis_view              func_wc \
    -power_switch_eco           true \
    -generate_decap_eco         true \
    -decap_opt_method           feasibility \
    -generate_movies            true \
    -save_voltage_waveforms     true \
    -accuracy                   hd \
    -temperature			125 \
    -gif_resolution             0 \
    -power_grid_library { \
	../Library/pgv/techonly.cl \
	../Library/pgv/stdcells.cl \

    }

We define the power (VDD) and ground (VSS) nets along with their voltage thresholds and sets up a rail analysis domain—just as in the static case.

set_pg_nets -net VDD     	-voltage 0.9 -threshold 0.05  -force
set_pg_nets -net VSS        	-voltage 0.0 -threshold 0.05  -force
set_rail_analysis_domain -name PD_default -pwrnets VDD -gndnets VSS

Then the definition of the power pad locations:

set_power_pads \
    -reset

set_power_pads \
    -net                        VDD \
    -format                     xy \
    -file                       VDD.pp

set_power_pads \
    -net                        VSS \
    -format                     xy \
    -file                       VSS.pp

Now run the dynamic rail analysis. It first resets previous power data and simulation settings, sets a timing resolution of 50ps, and loads dynamic current waveform data for VDD and VSS. It then runs the dynamic rail analysis for the power domain PD_default and outputs the results to the dynVecLessRailResults directory, followed by generating a power report in dynrail.rpt

set_power_data \
    -reset

set_dynamic_rail_simulation -reset
set_dynamic_rail_simulation -resolution 50ps

set_power_data \
    -format                     current \
    { \
	dynVecLessPowerResults/dynamic_VDD.ptiavg \
	dynVecLessPowerResults/dynamic_VSS.ptiavg \
    }

analyze_rail \
    -output          ./dynVecLessRailResults \
    -type                       domain \
				PD_default


report_power \
    -outfile                    dynrail.rpt

Open the voltage waveform for the instance alu_sra_4458_52_g4770 from the dynamic rail analysis results, allowing the user to visually inspect the voltage drop over time based on the simulation data.

view_dynamic_waveform \
-type voltage \
-instance_name alu_sra_4458_52_g4770 \
-waveform_files {./dynVecLessRailResults/PD_default_125C_dynamic_1/VDD/voltus_rail.tran.ptiavg }

It should look something like this for the VDD pad: